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NCP3163, NCV3163 3.4 A, Step-Up/Down/ Inverting 50-300 kHz Switching Regulator
The NCP3163 Series is a performance enhancement to the popular MC33163 and MC34163 monolithic DC-DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This controller was specifically designed to be incorporated in step-down, step-up, or voltage-inverting applications with a minimum number of external components. The NCP3163 comes in an exposed pad package which can greatly increase the power dissipation of the built in power switch.
Features http://onsemi.com MARKING DIAGRAMS
16 1 SOIC-16W EXPOSED PAD PW SUFFIX CASE 751AG NCx3163yPW AWLYYWWG 1 16
* * * * * * * * * * * * * *
Output Switch Current in Excess of 3.0 A 3.4 A Peak Switch Current Frequency is Adjustable from 50 kHz to 300 kHz Operation from 2.5 V to 40 V Input Externally Adjustable Operating Frequency Precision 2% Reference for Accurate Output Voltage Control Driver with Bootstrap Capability for Increased Efficiency Cycle-by-Cycle Current Limiting Internal Thermal Shutdown Protection Low Voltage Indicator Output for Direct Microprocessor Interface Exposed Pad Power Package Low Standby Current NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes These are Pb-Free Devices
Current Limit
18
1 NCP3163y AWLYYWW G G
18
1
18-LEAD DFN MN SUFFIX CASE 505
NCx3163x
8 Vin + Cin 6
- +
9
A WL YY WW G or G
= Specific Device Code x = P or V y = blank or B = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) 10
7 VCC Oscillator R Q 4 3 Thermal VCC S
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet.
11
5
12
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
13 14
2
+ + -
+ + -
15
1 LVI
16 VCC (Bottom View) CO Vout +
Figure 1. Typical Buck Application Circuit
(c) Semiconductor Components Industries, LLC, 2007
1
January, 2007 - Rev. 4
Publication Order Number: NCP3163/D
NCP3163, NCV3163
0.25 V
- +
IPKsense RSC VCC Timing Capacitor CT Shutdown RDT
8
Current Limit
9
Driver Collector
7 VCC 6 Oscillator R Q 4 3 45 k 2.0 mA Thermal S Latch VCC Q1 Q2
10 Switch Collector 11
5
12 60 13 14 Switch Emitter 15
Gnd Voltage Feedback 1
Voltage Feedback 2
2
+ + -
LVI Output
1 LVI
Feedback Comparator 1.25 V 15 k 7.0 V 1.125 V (Bottom View) VCC
+ + -
16
Bootstrap Input
+ -
= Sink Only Positive True Logic
Figure 2. Representative Block Diagram PIN FUNCTION DESCRIPTION
SOIC16 1 2 3 4 6 7 8 9 10,11 14,15 16 5,12,13 Exposed Pad DFN18 15 16 17 18 1 3 4 5 6,7,8,9 10,11,12,13 14 2 Exposed Pad PIN NAME LVI Output Voltage Feedback 2 Voltage Feedback 1 GND Timing Capacitor VCC Ipk Sense Drive Collector Switch Collector Switch Emitter Bootstrap Input No Connect Exposed Pad DESCRIPTION This pin will sink current when FB1 and FB2 are less than the LVI threshold (Vth). Connecting this pin to a resistor divider off of the output will regulate the application according to the Vout design equation in Figure 22. Connecting this pin directly to the output will regulate the device to 5.05 V. Ground pin for all internal circuits and power switch. Connect a capacitor to this pin to set the frequency. The addition of a parallel resistor will decrease the maximum duty cycle and increase the frequency. Power pin for the IC. When (VCC-VIPKsense) > 250 mV the circuit resets the output driver on a pulse by pulse basis. Voltage driver collector Internal switch transistor collector Internal switch transistor emitter Connect this pin to VCC for operation at low VCC levels. For some topologies, a series resistor and capacitor can be utilized to improve the converter efficiency. These pins have no connection. The exposed pad beneath the package must be connected to GND (pin 4). Additionally, using proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities of the NCP3163.
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MAXIMUM RATINGS (Note 1)
Rating Power Supply Voltage Switch Collector Voltage Range Switch Emitter Voltage Range Switch Collector to Emitter Voltage Switch Current Driver Collector Voltage (Pin 8) Driver Collector Current (Pin 8) Bootstrap Input Current Range Current Sense Input Voltage Range Feedback and Timing Capacitor Input Voltage Range Low Voltage Indicator Output Voltage Range Low Voltage Indicator Output Sink Current Power Dissipation and Thermal Characteristics Thermal Characteristics Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Air Storage Temperature Range Maximum Junction Temperature Operating Ambient Temperature (Note 3) NCP3163PW NCP3163BPW NCV3163PW C/W RqJC RqJA Tstg TJmax TA 0 to +70 -40 to +85 -40 to +125 15 56 -65 to +150 +150 C C C Symbol VCC VCSW VESW VCESW ISW VCC ICC IBST VIPKSNS Vin VCLVI ICLVI Value 0 to +40 -1.0 to +40 -2.0 to +40 +40 3.4 -1.0 to +40 150 -100 to +100 (VCC - 7.0) to (VCC + 1.0) -1.0 to +7.0 -1.0 to +40 10 Unit V V V V A V mA mA V V V mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1500 V per MIL-STD-883, Method 3015. Machine Model Method 150 V. 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded. 4. The pins which are not defined may not be loaded by external signals.
PIN CONNECTIONS
1 2 3 4 5 6 7 8 (Top View) Note: Pin 18 must be tied to EP Flag on PCB 16 15 14 13 12 11 10 9 Driver Collector Switch Collector N/C
LVI Output Voltage Feedback 2 Voltage Feedback 1 GND N/C Timing Capacitor VCC Ipk Sense
Bootstrap Input Switch Emitter Timing Capacitor N/C VCC Ipk Sense Driver Collector Switch Collector Switch Collector Switch Collector Switch Collector 1 2 3 4 5 6 7 8 9 18 GND 17 16 15 14 13 12 11 10 GND Voltage Feedback 1 Voltage Feedback 2 LVI Output Bootstrap Input Switch Emitter Switch Emitter Switch Emitter Switch Emitter
EP Flag
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ELECTRICAL CHARACTERISTICS (VCC = 15 V, Pin 16 = VCC, CT = 270 pF, RT = 15 kW, for typical values TA = 25C, for min/max
values TA is the operating ambient temperature range that applies (Note 7), unless otherwise noted.) Characteristic OSCILLATOR Frequency TA = 25C, VCC = 15 V Total Variation over VCC = 2.5 V to 40 V and Temperature Charge Current Discharge Current Charge to Discharge Current Ratio Sawtooth Peak Voltage Sawtooth Valley Voltage FEEDBACK COMPARATOR 1 Threshold Voltage TA = 25C Total Variation over VCC = 2.5 V to 40 V and Temperature Threshold Voltage Line Regulation (VCC = 2.5 V to 40 V, TA = 25C) Input Bias Current (VFB1 = 5.05 V) FEEDBACK COMPARATOR 2 Threshold Voltage TA = 25C, VCC = 15 V Total Variation over VCC = 2.5 V to 40 V and Temperature Threshold Voltage Line Regulation (VCC = 2.5 V to 40 V, TA = 25C) Input Bias Current (VFB2 = 1.25 V) CURRENT LIMIT COMPARATOR Threshold Voltage TA = 25C Total Variation over VCC = 2.5 V to 40 V, and Temperature Input Bias Current (VIpk (Sense) = 15 V) DRIVER AND OUTPUT SWITCH (Note 6) Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded) NCP3163 - Non-Darlington (RPin 9 = 110 W to VCC, ISW/IDRV 20) NCV3163 - Non-Darlington (RPin 9 = 110 W to VCC, ISW/IDRV 20) Darlington Connection (Pins 9, 10, 11 connected) Collector Off-State Leakage Current (VCE = 40 V) Bootstrap Input Current Source (VBS = VCC + 5.0 V) Bootstrap Input Zener Clamp Voltage (IZ = 25 mA) LOW VOLTAGE INDICATOR Input Threshold (VFB2 Increasing) Input Hysteresis (VFB2 Decreasing) Output Sink Saturation Voltage (Isink = 2.0 mA) Output Off-State Leakage Current (VOH = 15 V) TOTAL DEVICE Standby Supply Current (VCC = 2.5 V to 40 V, Pin 8 = VCC, Pins 6, 14, 15 = GND, remaining pins open) ICC - 6.0 10 mA Vth VH VOL(LVI) IOH 1.07 - - - 1.125 15 0.15 0.01 1.18 - 0.4 5.0 V mV V mA VCE(sat) - - - IC(off) Isource(DRV) VZ - 0.5 VCC + 6.0 0.6 0.6 1.0 0.02 2.0 VCC + 7.0 1.0 1.2 1.4 100 4.0 VCC + 9.0 mA mA V V Vth(Sense) - 225 IIB(Sense) - 250 - 1.0 - 270 20 mA mV Vth(FB2) 1.225 1.213 REGline(FB1) - IIB(FB2) - 0.4 0.008 - 0.03 0.4 mA 1.25 - 1.275 1.287 %/V V Vth(FB1) 4.9 4.85 REGline(FB1) - IIB(FB1) - 0.008 100 0.03 200 mA 5.05 - 5.2 5.25 %/V V fOSC 225 212 Ichg Idischg Ichg/Idischg VOSC(P) VOSC(V) - - 8.0 - - 250 250 225 25 9.0 1.25 0.55 275 288 - - 10.5 - - mA mA - V V kHz Symbol Min Typ Max Unit
5. Maximum package power dissipation limits must be observed. 6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 7. Tlow = 0C for NCP3163 Thigh = + 70C for NCP3163 = - 40C for NCP3163B = + 85C for NCP3163B = - 40C for NCV3163 = + 125C for NCV3163
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300 VCC = 15 V TA = 25C 250 FREQUENCY (kHz)
200 Rt = 15 kW 150 Rt = open 100 50 0 100 200 300 400 500 CT, TIMER CAPACITANCE (pF) 600 700
Figure 3. Oscillator Frequency vs. Timer Capacitance (CT)
f OSC, OSCILLATOR FREQUENCY CHANGE (%)
2.0 VCC = 15 V CT = 620 pF 0
f OSC, OSCILLATOR FREQUENCY CHANGE (%)
4.0 2.0 0 - 2.0 - 4.0 - 6.0 - 8.0 - 10 - 50 - 25 0 25 50 TEMPERATURE (C) 75 100 125 VCC = 15 V CT = 230 pF RT = 20 kW
- 2.0
- 4.0
- 6.0 - 55
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 4. Oscillator Frequency Change vs. Temperature when only CT is connected to Pin 6
Figure 5. Oscillator Frequency Change vs. Temperature when CT and RT are connected to Pin 6
140 IIB , INPUT BIAS CURRENT ( A) VCC = 15 V VFB1 = 5.05 V 120
V th(FB2), COMPARATOR 2 THRESHOLD VOLTAGE (mV)
1300 1280 1260 1240 Vth Min = 1225 mV 1220 1200 - 55 VCC = 15 V Vth Max = 1275 mV
Vth Typ = 1250 mV
100
80
60 - 55
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 6. Feedback Comparator 1 Input Bias Current vs. Temperature
Figure 7. Feedback Comparator 2 Threshold Voltage vs. Temperature
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NCP3163, NCV3163
I source (DRV), BOOTSTRAP INPUT CURRENT SOURCE (mA V Z, BOOTSTRAP INPUT ZENER CLAMP VOLTAGE (V 2.8 VCC = 15 V Pin 16 = VCC + 5.0 V 2.4 7.6 IZ = 25 mA 7.4
2.0
7.2
1.6
7.0
1.2 - 55
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
6.8 - 55
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 8. Bootstrap Input Current Source vs. Temperature
Figure 9. Bootstrap Input Zener Clamp Voltage vs. Temperature
0 VCE (sat), SOURCE SATURATION (V) VCE (sat), SINK SATURATION (V) VCC - 0.4 - 0.8 -1.2 -1.6 - 2.0 Darlington Configuration Emitter Sourcing Current to GND Pins 7, 8, 10, 11 = VCC Pins 4, 5, 12, 13 = GND TA = 25C, (Note 2)
1.2 1.0 0.8 0.6 0.4 0.2 0 Grounded Emitter Configuration Collector Sinking Current From VCC Pins 7, 8 = VCC = 15 V Pins 4, 5, 12, 13, 14, 15 = GND TA = 25C, (Note 2) Saturated Switch, RPin9 = 110 W to VCC GND 0 0.8 1.6 2.4 IC, COLLECTOR CURRENT (A) 3.2 Darlington, Pins 9, 10, 11 Connected
Bootstrapped, Pin 16 = VCC + 5.0 V
Non-Bootstrapped, Pin 16 = VCC 0 0.8 2.4 1.6 IE, EMITTER CURRENT (A) 3.2
Figure 10. Output Switch Source Saturation vs. Emitter Current
Figure 11. Output Switch Sink Saturation vs. Collector Current
V OL (LVI) , OUTPUT SATURATION VOLTAGE (V)
0 GND V E , EMITTER VOLTAGE (V) - 0.4 - 0.8 - 1.2 - 1.6 - 2.0 - 55 IC = 10 mA VCC = 15 V Pins 7, 8, 9, 10, 16 = VCC Pins 4, 6 = GND Pin 14 Driven Negative - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 IC = 10 mA
0.5 0.4 0.3 0.2 0.1 0
VCC = 5 V TA = 25C
0
2.0 4.0 6.0 Isink, OUTPUT SINK CURRENT (mA)
8.0
Figure 12. Output Switch Negative Emitter Voltage vs. Temperature
Figure 13. Low Voltage Indicator Output Sink Saturation Voltage vs. Sink Current
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V th (Ipk Sense) , THRESHOLD VOLTAGE (mV IIB (Sense), INPUT BIAS CURRENT ( A) 254 VCC = 15 V 1.6 1.4 1.2 1.0 0.8 0.6 - 55 VCC = 15 V VIpk (Sense) = 15 V
252
250
248
246 - 55
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 14. Current Limit Comparator Threshold Voltage vs. Temperature
Figure 15. Current Limit Comparator Input Bias Current vs. Temperature
8.0 I CC, SUPPLY CURRENT (mA) I CC, SUPPLY CURRENT (mA)
7.2 VCC = 15 V Pins 7, 8, 16 = VCC Pins 4, 6, 14 = GND Remaining Pins Open
6.0
6.4
4.0 Pins 7, 8, 16 = VCC Pins 4, 6, 14 = GND Remaining Pins Open TA = 25C 0 10 20 30 VCC, SUPPLY VOLTAGE (V) 40
5.6
2.0
4.8
0
4.0 - 55
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 16. Standby Supply Current vs. Supply Voltage
V CC(min) , MINIMUM OPERATING SUPPLY VOLTAGE (V)
Figure 17. Standby Supply Current vs. Temperature
3.0 2.6 2.2 1.8 1.4 1.0 - 55 Pin 16 Open
CT = 620 pF Pins 7,8 = VCC Pins 4, 14 = GND Pin 9 = 1.0 kW to 15 V Pin 10 = 100 W to 15 V
Pin 16 = VCC
- 25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
Figure 18. Minimum Operating Supply Voltage vs. Temperature
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INTRODUCTION The NCP3163 is a monolithic power switching regulator optimized for DC-to-DC converter applications. The combination of its features enables the system designer to directly implement step-up, step-down, and voltage- inverting converters with a minimum number of external components. Potential applications include cost sensitive consumer products as well as equipment for the automotive, computer, and industrial markets. A representative block diagram is shown in Figure 2. OPERATING DESCRIPTION The NCP3163 operates as a fixed on-time, variable off-time voltage mode ripple regulator. In general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. The Typical Operating Waveforms are shown in Figure 19. The output voltage waveform shown is for a step-down converter with the ripple and phasing exaggerated for clarity. During initial converter startup, the feedback comparator senses that the output voltage level is below nominal. This causes the output switch to turn on and off at a frequency and duty cycle controlled by the oscillator, thus pumping up the output filter capacitor. When the output voltage level reaches nominal, the feedback comparator sets the latch, immediately terminating switch conduction. The feedback comparator will inhibit the switch until the load current causes the output voltage to fall below nominal. Under these conditions, output switch conduction can be inhibited for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles.
Oscillator
The oscillator frequency and on-time of the output switch are programmed by the value selected for timing capacitor CT. Capacitor CT is charged and discharged by a 9 to 1 ratio internal current source and sink, generating a negative going sawtooth waveform at Pin 6. As CT charges, an internal pulse is generated at the oscillator output. This pulse is connected to the NOR gate center input, preventing output switch conduction, and to the AND gate upper input, allowing the latch to be reset if the comparator output is low. Thus, the output switch is always disabled during ramp-up and can be enabled by the comparator output only at the start of ramp-down. The oscillator peak and valley thresholds are 1.25 V and 0.55 V, respectively, with a charge current of 225 mA and a discharge current of 25 mA, yielding a maximum on-time duty cycle of 90%. A reduction of the maximum duty cycle may be required for specific converter configurations. This can be accomplished with the addition of an external deadtime resistor (RDT) placed across CT. The resistor increases the discharge current which reduces the on-time of the output switch. The converter output can be inhibited by clamping CT to ground with an external NPN small-signal transistor. To calculate the frequency when only CT is connected to Pin 6, use the equations found in Figure 22. When RT is also used, the frequency and maximum duty cycle can be calculated with the NCP3163 design tool found at www.onsemi.com.
1 Comparator Output 0 1.25 V Timing Capacitor CT 0.55 V 1 Oscillator Output 0 On Output Switch Off Nominal Output Voltage Level t 9t
Output Voltage
Startup
Quiescent Operation
Figure 19. Typical Operating Waveforms
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Feedback and Low Voltage Indicator Comparators
Output voltage control is established by the Feedback comparator. The inverting input is internally biased at 1.25 V and is not pinned out. The converter output voltage is typically divided down with two external resistors and monitored by the high impedance noninverting input at Pin 2. The maximum input bias current is 0.4 mA, which can cause an output voltage error that is equal to the product of the input bias current and the upper divider resistance value. For applications that require 5.0 V, the converter output can be directly connected to the noninverting input at Pin 3. The high impedance input, Pin 2, must be grounded to prevent noise pickup. The internal resistor divider is set for a nominal voltage of 5.05 V. The additional 50 mV compensates for a 1.0% voltage drop in the cable and connector from the converter output to the load. The Feedback comparator's
output state is controlled by the highest voltage applied to either of the two noninverting inputs. The Low Voltage Indicator (LVI) comparator is designed for use as a reset controller in microprocessor-based systems. The inverting input is internally biased at 1.125 V, which sets the noninverting input thresholds to 90% of nominal. The LVI comparator has 15 mV of hysteresis to prevent erratic reset operation. The Open Collector output is capable of sinking in excess of 6.0 mA (see Figure 13). An external resistor (RLVI) and capacitor (CDLY) can be used to program a reset delay time (tDLY) by the formula shown below, where Vth(MPU) is the microprocessor reset input threshold. Refer to Figure 20.
1 Vth(MPU) 1- Vout
tDLY = RLVI CDLY In
3 2 Low Voltage Indicator Output RLVI 1 CDLY LVI
+ + - + + -
14 Feedback Comparator 15 16 L CO Vout
1.25 V 1.125 V
(Bottom View)
Figure 20. Partial Application Schematic Showing Implementation of LVI Delay with RLVI and CDLY Current Limit Comparator, Latch and Thermal Shutdown
With a voltage mode ripple converter operating under normal conditions, output switch conduction is initiated by the oscillator and terminated by the Voltage Feedback comparator. Abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. Under these conditions, the Current Limit comparator will protect the Output Switch. The switch current is converted to a voltage by inserting a fractional ohm resistor, RSC, in series with VCC and output switch transistor Q2. The voltage drop across RSC is monitored by the Current Sense comparator. If the voltage drop exceeds 250 mV with respect to VCC, the comparator will set the latch and terminate output switch conduction on a cycle-by-cycle basis. This Comparator/Latch configuration ensures that the Output Switch has only a single on-time during a given oscillator cycle. The calculation for a value of RSC is:
RSC + 0.25 V Ipk (Switch)
200 ns. The parasitic inductance associated with RSC and the circuit layout should be minimized. This will prevent unwanted voltage spikes that may falsely trip the Current Limit comparator. Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. When activated, typically at 170C, the Latch is forced into the "Set" state, disabling the Output Switch. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a replacement for proper heatsinking.
Driver and Output Switch
Figures 14 and 15 show that the Current Sense comparator threshold is tightly controlled over temperature and has a typical input bias current of 1.0 mA. The propagation delay from the comparator input to the Output Switch is typically
To aid in system design flexibility and conversion efficiency, the driver current source and collector, and output switch collector and emitter are pinned out separately. This allows the designer the option of driving the output switch into saturation with a selected force gain or driving it near saturation when connected as a Darlington. The output switch has a typical current gain of 70 at 2.5 A and is designed to switch a maximum of 40 V collector to emitter, with up to 3.4 A peak collector current. The minimum value for RSC is:
RSC(min) + 0.25 V + 0.0735 W 3.4 A
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When configured for step-down or voltage-inverting applications (see application notes at the end of this document) the inductor will forward bias the output rectifier when the switch turns off. Rectifiers with a high forward voltage drop or long turn-on delay time should not be used. If the emitter is allowed to go sufficiently negative, collector current will flow, causing additional device heating and reduced conversion efficiency. Figure 12 shows that by clamping the emitter to 0.5 V, the collector current will be in the range 10 mA over temperature. A 1N5822 or equivalent Schottky barrier rectifier is recommended to fulfill these requirements. A bootstrap input is provided to reduce the output switch saturation voltage in step-down and voltage-inverting converter applications. This input is connected through a series resistor and capacitor to the switch emitter and is used to raise the internal 2.0 mA bias current source above VCC. An internal zener limits the bootstrap input voltage to VCC +7.0 V. The capacitor's equivalent series resistance must limit the zener current to less than 100 mA. An additional series resistor may be required when using tantalum or other
Vias to 2nd Layer Metal for Maximum Heat Sinking Exposed Pad 0.175
low ESR capacitors. The equation below is used to calculate a minimum value bootstrap capacitor based on a minimum zener voltage and an upper limit current source.
t CB(min) + I Dt + 4.0 mA on + 0.001 ton DV 4.0 V
Parametric operation of the NCP3163 is guaranteed over a supply voltage range of 2.5 V to 40 V. When operating below 3.0 V, the Bootstrap Input should be connected to VCC. Figure 18 shows that functional operation down to 1.7 V at room temperature is possible.
Package
The NCP3163 is contained in a heatsinkable 16-lead plastic package in which the die is mounted on a special heat tab copper alloy pad. This pad is designed to be soldered directly to a GND connection on the printed circuit board to improve thermal conduction. Since this pad directly contacts the substrate of the die, it is important that this pad be always soldered to GND, even if surface mount heat sinking is not being used. Figure 21 shows recommended layout techniques for this package.
0.188
Minimum Recommended Exposed Copper
0.145
Flare Metal for Maximum Heat Sinking
Figure 21. Layout Guidelines to Obtain Maximum Package Power Dissipation
APPLICATIONS Figures 23 through 30 show the simplicity and flexibility of the NCP3163. Three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. Figure 22 gives the relevant design equations for the key parameters. Additionally, a complete application design aid for the NCP3163 can be found at www.onsemi.com.
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NCP3163, NCV3163
Calculation (See Notes 1,2,3) ton toff Step-Down V out ) V F * V sat * V out in t on t off ton t on )1 t off Step-Up V out ) V F - V in V - V sat in t on t off t on )1 t off Voltage-Inverting |V out| ) V F V * V sat in t on t off t on )1 t off
V
CT IL(avg) Ipk (Switch) RSC
32.143 * 10*6 * 20 @ 10 *12 f Iout IL(avg) ) DI L 2
32.143 * 10*6 * 20 @ 10 *12 f I out t on )1 t off DI L 2
32.143 * 10*6 * 20 @ 10 *12 f I out t on )1 t off DI L 2
IL(avg) )
IL(avg) )
0.25 Ipk (Switch) V in * V sat * V out DI L 1 8 CO V 2 ) (ESR)2 V t on
0.25 Ipk (Switch) in * V sat DI L t on I out C R2 ref R1 O )1 V V t on
0.25 Ipk (Switch) in * V sat DI L t on I out C R2 ref R1 O )1 t on
L
Vripple(pp)
DIL
[
[
Vout
R2 ref R1
)1
V
The following Converter Characteristics must be chosen: Nominal operating input voltage. Desired output voltage. Desired output current. Desired peak-to-peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce converter output current capability. p - Maximum output switch frequency. Vripple(pp) - Desired peak-to-peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. NOTES: NOTES: NOTES: NOTES: 1. 2. 3. 3. Vsat - Saturation voltage of the output switch, refer to Figures 10 and 11. VF - Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum operating input voltage. Vin - Vout - Iout - DIL -
Figure 22. Design Equations
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NCP3163, NCV3163
0.25 V
- +
8 RSC Vin Cin 7
Current Limit
9 10
VCC 6 Oscillator R Q S Latch VCC 45 k Q1 Q2 12 60 13 14
+ + - + + -
11
RT
CT 5 Thermal 4 3 R1 2 R2 1 LVI Feedback Comparator
15 2.0 mA 16
D
1.25 V 15 k 1.125 V VCC
7.0 V
CB
RB
L CO Vout
(Bottom View)
Figure 23. Typical Buck Application Schematic Value of Components
Name L D Cin Cout Ct Rt Value 47 mH 2 A, 40 V Schottky Rectifier 47 mF, 35 V 100 mF, 10 V 270 pF 10% 15 kW R1 R2 Rsc Cb Rb Name Value 15 kW 24.9 kW 80 mW, 1 W 4.7 nF 200 W
Test Results for Vout = 3.3 V
Test Line Regulation Load Regulation Output Ripple Efficiency Short Circuit Current Condition Vin = 8.0 V to 24 V, Iout = 2.5 A Vin = 12 V, Iout = 0 to 2.5 A Vin = 12 V, Iout = 0 to 2.5 A Vin = 12 V, Iout = 2.5 A Vin = 12 V, RL = 0.1 W Results 13 mV 25 mV 100 mVpp 70.3% 3.1 A
Test Results for Vout = 5.05 V
Test Line Regulation Load Regulation Output Ripple Efficiency Short Circuit Current Condition Vin = 10.2 V to 24 V, Iout = 2.5 A Vin = 12 V, Iout = 0 to 2.5 A Vin = 12 V, Iout = 0 to 2.5 A Vin = 12 V, Iout = 2.5 A Vin = 12 V, RL = 0.1 W Results 54 mV 28 mV 150 mVpp 75.5% 3.1 A
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NCP3163, NCV3163
Figure 24. Buck Layout
APPLICATION SPECIFIC CHARACTERISTICS
85 5.0 V Eff 80 EFFICIENCY (%) 75 70 65 60 55 50 0 0.5 1.0 Iout (A) 1.5 2.0 2.5 3.3 V Eff
Figure 25. Efficiency vs. Output Current for the Buck Demo Board at Vin = 12 V, TA = 255C
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NCP3163, NCV3163
0.25 V
- +
8 RSC Vin Cin +7 6 RT CT 5
Current Limit
L 9 10
VCC Oscillator R Q S Latch VCC 45 k Q1 Q2 60 13 D 14
+ + - + + -
11 12
Thermal 4 3 2 1 LVI R1
Feedback Comparator 2.0 mA 7.0 V
15 16
1.25 V 15 k 1.125 V VCC
R2
(Bottom View)
CO
+
Vout
Figure 26. Typical Boost Application Schematic
Value of Components for Vout = 24 V
Name L D Cin Ct Rt Value 33 mH 2 A, 40 V Schottky Rectifier 330 mF, 35 V 270 pF 10% 15 kW R1 R2 Cout Rsc Name Value 42.2 kW 2.32 kW 330 mF, 25 V 80 mW, 1 W
Test Results for Vout = 24 V
Test Line Regulation Load Regulation Output Ripple Efficiency Short Circuit Current Condition Vin = 10 V to 20 V, Iout = 700 mA Vin = 12 V, Iout = 0 to 700 mA Vin = 12 V, Iout = 0 to 700 mA Vin = 12 V, Iout = 700 mA Vin = 12 V, RL = 0.1 W Results 90 mV 80 mV 300 mVpp 83% 3.1 A
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NCP3163, NCV3163
Figure 27. Boost Demo Board Layout
86 84 EFFICIENCY (%) 82 80 78 76 74 0.1
0.2
0.3
0.4 Iout (A)
0.5
0.6
0.7
Figure 28. Efficiency vs. Output Current for the Boost Demo Board at Vin = 12 V, TA = 255C
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NCP3163, NCV3163
0.25 V
- +
8 RSC Vin Cin
+
Current Limit
9 10
7 VCC 6 Oscillator R Q S Latch VCC 45 k 2 1 LVI R1
+ + - + + -
Q1 Q2 60
11 12 13 14
RT
CT 5 Thermal 4 3
L RB CB D + CO Vout
Feedback Comparator 2.0 mA VCC 7.0 V
15 16
1.25 V 15 k 1.125 V
R2
(Bottom View)
Figure 29. Typical Voltage Inverting Application Schematic Value of Components for Vout = -15 V
Name L D Cin Cout Ct Value 47 mH 2 A, 40 V Schottky Rectifier 270 mF, 16 V 2 X 270 mF, 16 V 150 pF 10% R1 R2 Rsc Cb Rb Name Value 1.07 kW 11.8 kW 80 mW, 1 W 4.7 nF 200 mW
Test Results for Vout = -15 V
Test Line Regulation Load Regulation Output Ripple Efficiency Short Circuit Current Condition Vin = 7.0 V to 16 V, Iout = 500 mA Vin = 12 V, Iout = 0 to 500 mA Vin = 12 V, Iout = 0 to 500 mA Vin = 12 V, Iout = 500 mA Vin = 12 V, RL = 0.1 W Results 35 mV 20 mV 100 mVpp 68% 3.1 A
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NCP3163, NCV3163
Figure 30. Voltage Inverting Demo Board Layout
70
66 EFFICIENCY (%)
62
58
54 50 0.1
0.15
0.2
0.25
0.3 Iout (A)
0.35
0.4
0.45
0.5
Figure 31. Efficiency vs. Output Current for the Voltage Inverting Demo Board at Vin = 12 V, TA = 255C
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NCP3163, NCV3163
ORDERING INFORMATION
Device NCP3163PWG NCP3163PWR2G NCP3163BPWG NCP3163BPWR2G NCP3163MNR2G NCP3163BMNR2G NCV3163PWG NCV3163PWR2G Package SOIC-16 W Exposed Pad (Pb-Free) SOIC-16 W Exposed Pad (Pb-Free) SOIC-16 W Exposed Pad (Pb-Free) SOIC-16 W Exposed Pad (Pb-Free) DFN18 (Pb-Free) DFN18 (Pb-Free) SOIC-16 W Exposed Pad (Pb-Free) SOIC-16 W Exposed Pad (Pb-Free) Shipping 47 Units / Rail 1000 / Tape & Reel 47 Units / Rail 1000 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 47 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP3163, NCV3163
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY, EXPOSED PAD PW SUFFIX CASE 751AG-01 ISSUE O
-U- A M
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.31 3.51 0.25 0.32 0.00 0.10 4.58 4.78 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.130 0.138 0.010 0.012 0.000 0.004 0.180 0.188 0_ 7_ 0.395 0.415 0.010 0.029
P 0.25 (0.010)
M
W
M
1 8
B R x 45_ -W-
PIN 1 I.D.
G TOP SIDE
14 PL
DETAIL E
C -T- 0.10 (0.004) T D 16 PL 0.25 (0.010) H
M
F
K TU
S
SEATING PLANE
W
S
J DETAIL E
DIM A B C D F G H J K L M P R
EXPOSED PAD
1
8
SOLDERING FOOTPRINT*
L 0.350 0.175 0.050 Exposed Pad
16
9
BACK SIDE C L 0.200 0.074 0.188 C L 0.376
0.024
0.145
DIMENSIONS: INCHES
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP3163, NCV3163
PACKAGE DIMENSIONS
DFN18 CASE 505-01 ISSUE D
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.45 0.65
PIN 1 LOCATION
E
2X
0.15 C
2X
0.15 C 0.10 C
18X
TOP VIEW (A3) A
0.08 C SIDE VIEW D2
18X
A1
C
SEATING PLANE
SOLDERING FOOTPRINT*
5.30
18X
L
e
1 9
1
0.75
18X
K
18 10
E2
0.50 PITCH
4.19
18X
BOTTOM VIEW
b 0.10 C A B 0.05 C
NOTE 3
18X
0.30
3.24
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP3163/D

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